Pseudo-ops Listed by Opcode

The table that follows lists the assembly language pseudo-ops for the Itanium(TM) architecture according to their opcodes. The table lists pseudo-ops with missing operands. The opcodes are listed alphabetically, with their operands, and the equivalent machine instructions. The table lists mnemonics converted to other mnemonics.

Opcode

Instruction Description

Operands

Equivalent Machine Instruction

add

 

Add immediate

r1 =imm,r3

adds    r1 =imm14,r3

addl    r1 =imm22,r3

break  

Break

imm21

break.b    imm21 (B)

break.i    imm21 (I)

break.m    imm21 (M)

break.f    imm21 (F)

chk.s   

Speculation check

r2,target25

chk.s.i    r2,target25(I)

chk.s.m    r2,target25(M)

fabs

 

Floating-point

absolute value

f1 =f3

fmerge.s   f1 =f0,f3

fadd.pc.sf

 

Floating-point add

f1 =f3,f2

fma.pc.sf f1 =f3,f1,f2

fcvt.xuf

 

Convert integer to float unsigned

f1 =f3

fma.pc.sf f1 =f3,f1,f0

fmpy.pc.sf

 

Floating-point

multiply

f1 =f3,f4

fma.pc.sf f1 =f3,f4,f0

fneg

 

Floating-point

negate

f1 =f3

fmerge.ns f1 =f3,f3

fnegabs

 

Floating-point

negate absolute

value

f1 =f3

fmerge.ns f1 =f0,f3

fnorm.pc.sf

 

Floating-point

normalize

f1 =f3

fma.pc.sf f1 =f3,f1,f0

fsub.pc.sf

 

Floating-point

subtract

f1 =f3,f2

fms.pc.sf f1 =f3,f1,f2

ld8.mov

ld8 that can be translated to mov.  It is used to support link time rewriting of indirect addressing code sequences. In ELF format only.

r2=[r3],

Symbol+Addend

ld8 r2=[r3]

mov r2=r3

mov

 

Move to application register

immediate

ar3 =imm8

mov.i      ar3 =imm8 (I)

mov.m      ar3 =imm8 (M)

mov

 

Move to application register

ar3 =r2

mov.i      ar3 =r2 (I)

mov.m      ar3 =r2 (M)

mov

 

Move

floating-point

register

f1 =f3

fmerge.s   f1 =f3,f3

mov

 

Move from application register

r1 =ar3

mov.i      r1 =ar3 (I)

mov.m      r1 =ar3 (M)

mov   

Move immediate

r1 =imm22

addl       r1 =imm22,r0

mov

 

Move general

register

r1 =r2

adds       r1 =0,r2

mov

 

Move to branch

register

b1 =r2

mov        b1 =r2

nop  

No operation

imm21

nop.b      imm21 (B)

nop.i      imm21 (I)

nop.m      imm21 (M)

nop.f      imm21 (F)

shl  

Shift left

r1=r2,count6

dep.z      r1=r2,count6,
     64-count6

shr  

Shift right signed

r1=r3,count6

extr       r1=r3,count6,
     64-count6

shr.u

 

Shift right unsigned

r1=r3,count6

extr.u     r1=r3,count6,
     64-count6

xma.lu

 

 Fixed-point

multiply low

unsigned

f1=f2,f3,f4,

 

xma.l   f1 =f2,f3,f4